One of the core competencies of ACTL is the test and diagnosis of failing ICs. We specialize in developing state-of-the-art test and diagnosis methodologies for advanced-node circuits. One unique capability of our lab is the design of logic characterization vehicles (i.e., test chips) that are both transparent to failure and reflective of real-world designs. Over 60 of our test-chip designs have been fabricated in various technology nodes, including 7nm, and data collected from a large volume of chips is being routinely analyzed.
  1. Q. Huang, C. Fang, S. Mittal and R. D. Blanton, "Improving Diagnosis Efficiency via Machine Learning," in International Test Conference, Nov. 2018.[PDF]

  2. Z. Liu and R. D. Blanton, "Back-End Layout Reflection for Test Chip Design," IEEE International Conference on Computer Design, Oct. 2018.[PDF]

  3. Y. Xue, X. Li and R. D. Blanton, "Improving Diagnostic Resolution of Failing ICs Through Learning," IEEE Transactions on CAD, June 2018.[PDF]

  4. S. Mittal and R. D. Blanton, "NOIDA: Noise-resistant Intra-cell Diagnosis," IEEE VLSI Test Symposium, April 2018.[PDF]

  5. S. Mittal and R. D. Blanton, "PADLOC: Physically-Aware Defect Localization and Characterization," IEEE Asian Test Symposium, Nov. 2017.[PDF]

  6. Z. Liu, P. Fynan, and R. D. Blanton, "Front-End Layout Reflection for Test chip Design," IEEE International Test Conference, Oct.-Nov. 2017.[PDF]

  7. B. Niewenhuis, S. Mittal and R. D. Blanton, "Multiple-Defect Diagnosis for Logic Characterization Vehicles," IEEE European Test Symposium, May 2017.[PDF]

  8. C. Xue and R. D. Blanton, "Test-set Reordering for Improving Diagnosability," IEEE VLSI Test Symposium, April 2017.[PDF]

  9. S. Mittal, Z. Liu, B. Niewenhuis and R. D. Blanton, "Test Chip Design for Optimal Cell-Aware Diagnosability", IEEE International Test Conference, Nov. 2016. [PDF]

  10. Z. Liu, S. Mittal, B. Niewenhuis and R. D. Blanton, "Achieving 100% Cell-Aware Coverage by Design", Design, Test and Automation in Europe, March 2016. [PDF]

Lab Members
| Graduate Students |
Zeye Liu
     Logic Test Chip 
Soumya Mittal
     Circuit Diagnosis 
Qicheng Huang 
     Diagnosis Improvement 
Chenlei Fang 
     Diagnosis Improvement
Yield Learning
Advanced   Chip   
Test  Laboratory.

The Advanced Chip Test Laboratory (ACTL) at Carnegie Mellon University develops and implements data-mining techniques for improving the operation, design, manufacturing and testing of integrated systems. Our research involves data-mining algorithm development, data analysis, chip design and fabrication in collaboration with various industrial partners that currently include IBM, NVIDIA, Qualcomm, CISCO Systems, Intel, GlobalFoundries, and ARM. The founder and head of ACTL is Prof. Shawn Blanton.

Advanced Chip Test Laboratory,

5000 Forbes Ave, Pittsburgh,PA 15213-3890

Tel: 412.268.2987



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