Machine Learning
Description
Machine learning is now becoming a ubiquitous and necessary capability for all endeavors of engineering. In the Advanced Test Chip Laboratory, we use Machine Learning for defect characterization, failing IC diagnosis, IC testing, operational monitoring, and design characterization. In addition, we are making fundamental contributions to the area machine learning in the areas of acceleration and new algorithm development as well.
Publications
  1. C. Nguyen, X. Li, R. D. Blanton and X. Li "Partial Bayesian Co-training For Virtual Metrology," in IEEE Transactions on Industrial Informatics, Jan. 2019.[PDF]

  2. R. Ding, Z. Liu, R. D. Blanton and D. Marculescu, "Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs," in ACM Transactions on Reconfigurable Technology and Systems, 2018.[PDF]

  3. A. Goel, Z. Liu and R. D. Blanton, "CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation," IEEE International Conference on Big Data, 2018.[PDF]

  4. Q. Huang, C. Fang, S. Mittal and R. D. Blanton, "Improving Diagnosis Efficiency via Machine Learning," in International Test Conference, Nov. 2018.[PDF]

  5. R. Ding, Z. Liu, T. Chin, D. Marculescu and R. D. Blanton, "Differentiable Training for Hardware Efficient LightNNs," in NIPS 2018 workshop on Compact Deep Neural Networks with industrial applications, Dec. 2018.[PDF]

  6. C. Nguyen, X. Li, R. D. Blanton and X. Li "Partial Bayesian Co-training For Virtual Metrology," in IEEE International Conference on Emerging Technologies and Factory, 2017.[PDF]

  7. R. Ding, Z. Liu R. Shi, D. Marculescu and R. D. Blanton "LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks," ACM Great Lakes Symposium on VLSI, May 2017.[PDF]

  8. Y. Xue, C. Lim, M. E. Amyeen, X. Li, and R. D. Blanton, "Diagnostic Resolution Improvement through Learning-Guided Physical Failure Analysis", IEEE International Test Conference, Nov. 2016. [PDF]

  9. R. D. Blanton, F. Wang, C. Xue, Pk Nag, Y. Xue, and X. Li. "DREAMS: DFM Rule EvAluation Using Manufactured Silicon." International Conference on Computer-Aided Design, 2013. [PDF]

  10. Y. Xue, O. Poku, X. Li and R. D. Blanton, “PADRE: Physically-Aware Diagnostic Resolution Enhancement,” International Test Conference, Nov. 2013. [PDF]

Lab Members
| Graduate Students |
Zeye Liu
     DNN Hardware Quantization
Qicheng Huang
     ML Application on Diagnosis 
Chenlei Fang 
     ML Application on Diagnosis
Advanced   Chip   
Test  Laboratory.

The Advanced Chip Test Laboratory (ACTL) at Carnegie Mellon University develops and implements data-mining techniques for improving the operation, design, manufacturing and testing of integrated systems. Our research involves data-mining algorithm development, data analysis, chip design and fabrication in collaboration with various industrial partners that currently include IBM, NVIDIA, Qualcomm, CISCO Systems, Intel, GlobalFoundries, and ARM. The founder and head of ACTL is Prof. Shawn Blanton.

Advanced Chip Test Laboratory,

5000 Forbes Ave, Pittsburgh,PA 15213-3890

Tel: 412.268.2987

Email: rblanton@andrew.cmu.edu

ACTL .

© Copyrigh-Advanced Chip Test Laboratory.Updated 4/28/2019