Description

Global consolidation of the semiconductor industry has raised significant concerns about the security of integrated circuits. Issues that include counterfeiting, reverse engineering, malicious design alteration, data leakage, etc. are now all significant concerns for designers, fabricators, and users of integrated electronic systems. Research in the Advanced Test Chip Laboratory has multiple projects that address a variety of the challenges that arise when achieving secure, trustworthy systems based on integrated circuits.

Publications

1. X. Ren, F. P. Torres, R. D. Blanton and V. G. Tavares, "IC Protection Against JTAG-based Attacks," IEEE Transactions on CAD, Feb. 2018. [PDF]

2. X. Ren, R. D. Blanton and V. G. Tavares, "Detection of IJTAG Attacks Using LDPC-based Feature Reduction and Machine Learning", IEEE European Test Symposium, May 2018. [PDF]

3. X. Ren, R. D. Blanton and V. G. Tavares, "A Learning-based Approach to Secure JTAG against Unseen Scan-based Attacks", IEEE Computer Society Annual Symposium on VLSI, July 2016. [PDF]

4. X. Ren, V. G. Tavares, and R. D. Blanton. “Detection of Illegitimate Access to JTAG via Statistical Learning in Chip,” Design, Automation and Test in Europe, Mar 2015. [PDF]

5. B. Niewenhuis, R. D. Blanton, M. Bhargava, and K. Mai, “SCAN-PUF: A Low Overhead Physically Unclonable Function from Scan Chain Power-Up States,” International Test Conference, Nov. 2013. [PDF]

Lab Members

| Graduate Students |

- Danille Duvalsaint

     Logic Locking and Attacking 

- Ruben Purdy

     Circuit Obfuscation and Logic Locking

- Gustavo Camero 

     Machine Learning Security