People
Former Undergraduate Students

Raman Sharma

  • Project Title: DDQ Test Generation for Regular Circuits, Spring 1996

 

Anuj Agarwa

  • Project Title: ATPG for Regular Circuits, Summer 1996

 

Prakash Guda

  • Project Title: FSM Test Generation, Spring 1997

 

Brian Prasky

  • Project Title: ATPG for One Dimensional Arrays, Summer 1998

 

Nathan Drees

  • Project Title: On the Understanding of Crosstalk on Dynamic Logic Misbehavior, Summer 1999

 

John Gunter

  • Project Title: On the Understanding of Bridging Shorts on Dynamic Logic Misbehavior, Summer 1999

 

Michelle Kruvczuk

  • Project Title: Manufacturing Corner Analysis of New Dynamic Logic Families, Summer 1999

 

Adrian Drury

  • Project Title: Testing Digital Circuits on the Teradyne J941 VLSI IC Tester, Summer 1999

 

Reena Singhal

  • Project Title: Test Cost Modeling, Spring 2000

 

Michael Menietti

  • Project Title: BIST via Ring Counters, Fall 2000 and Spring 2001

 

Anirudh Shah

  • Project Title: Layout-based Neighbor Identification, Fall 2002 and Spring 2003

 

Emiko Oforitsenere

  • Project Title: Economic Yield Recovery Model for VPGA, Spring 2003

 

Nishant Patil

  • Project Title: Macrofault Modeling of Spot Contamination Induced Bridge Defects, Fall 2004

 

Derrick Losli

  • Project Title: Salvaging ALU Functionality via Behavioral Failure Diagnosis, Spring and Fall 2007

 

Henry Teng

  • Project Title: Statistical Analysis of Test Data, NSF REU, Summer 2007

 

Chukwuemeka Uchenna Ezekwe

  • Project Title: Test Relaxation for Physically-Aware N-Detect, Summer 2008

 

Ibrahima Komara

  • Project Title: Sensitivity Analysis of Diagnosis Accuracy on Fail Data Volume, Summer 2009

 

Chengjou Liao

  • Project Title: Limited Multiple Fault Analysis using Real Silicon Fail Data, Summer and Fall 2009

 

Chongzhe Li

  • Project Title: Diagnosis Sensitivity to Test Measurement Data Volume, Chinese Exchange Student, Fall 2009

 

Vincent Liu

  • Project Title: Sensitivity Analysis of Diagnosis Accuracy on Fail Data Volume, Summer 2010

 

Shonda Bell

  • Project Title: Physically-Aware Netlists, Summer 2010

 

Thomas Tzou

  • Project Title: Automatic Macrofault Generators, Spring and Summer 2010

 

Nancy Zhang

  • Project Title: Virtual Trojan Circuit Creation for FPGAs, Spring 2011

 

Martyn Romanko

  • Project Title: Fault Detection, Diagnosis, and Tolerance within ALUs, Summer 2010

 

Idryiys Harris

  • Project Title: Web-based Interface for Virtual Fail Data, Summer 2011

 

Saurabh Suryavanshi

  • Project Title: Trojan Detection in FPGAs, Summer 2011

 

Joe Zischkau

  • Project Title: Web-based Interface for Virtual Fail Data, Fall 2011 and Spring 2012

 

Harsh Shrivastava

  • Project Title: TRAX Fault Model Evaluation, Summer 2012

Solomon Sia

  • Project Title: Systematic Defect Identification, Summer 2013

 

Julian Binder

  • Project Title: FPGA Implementation of SLIC on FPGAs, Fall 2014 and Spring 2015.

 

DJ Park

  • Project Title: Implementation of Secure JTAG via Statistical Learning in Chip on a FPGA, Fall 2014 and Spring 2015.

 

Jaime Kang

  • Project Title: Physically-Aware Diagnosis of Defective FPGAs, Spring 2015.

 

Francisco Pimentel Torres

  • Project Title: FPGA Implementation of SLIC-J on FPGAs, Summer 2015.

 

César Carpinteiro

  • Project Title: FPGA Implementation of Dynamic KNN, Summer 2015.

 

Anthony Jin

  • Project Title: SCAN-PUF Silicon Data Analysis, Summer 2015.

 

Chad Malinowski

  • Project Title: Bijective Functional Analysis for Effective LCV Implementation, Summer 2015.

 

Paul Griffioen

  • Project Title: Robust Adder Design using LPDC, Summer 2015.

 

Nathan Slager

  • Project Title: Test Silicon Data Analysis for Fault Model Evaluation, Summer 2015.

 

Joey Fernau

  • Project Title: Interval Arithmetic for Video Game Enhancement, Summer 2015.

 

Rohan Saigal

  • Project Title: Deciphering the ENIGMA, Fall 2015.

 

Evaline Ju

  • Project Title: Hardware Implementation of BIG DATA Learning Algorithms, Spring 2016.

 

Abhinand Sukumar

  • Project Title: Hardware Optimization of Decision Tree Learning, Spring 2016.

 

Jonathan Engle

  • Project Title: Machine-Learning Based Test Validation Optimization, Summer 2016.

 

Andrew Davis

  • Project Title: Machine-Learning Based Test Validation Optimization, Summer 2016.

 

Aditya Ramesh

  • Project Title: Neural Network Hardware Implementation for Online Training and Usage, Summer 2016.

Advanced   Chip   
Test  Laboratory.

The Advanced Chip Test Laboratory (ACTL) at Carnegie Mellon University develops and implements data-mining techniques for improving the operation, design, manufacturing and testing of integrated systems. Our research involves data-mining algorithm development, data analysis, chip design and fabrication in collaboration with various industrial partners that currently include IBM, NVIDIA, Qualcomm, CISCO Systems, Intel, GlobalFoundries, and ARM. The founder and head of ACTL is Prof. Shawn Blanton.

Advanced Chip Test Laboratory,

5000 Forbes Ave, Pittsburgh,PA 15213-3890

Tel: 412.268.2987

Email: rblanton@andrew.cmu.edu

ACTL .

© Copyrigh-Advanced Chip Test Laboratory.Updated 4/28/2019