Publications

Other Papers

1. R. Ding, Z. Liu, R. D. Blanton and D. Marculescu, "Quantized Deep Neural Networks for Energy Efficient Hardware-based Inference (Invited Paper)," Asia and South Pacific Design Automation Conference, 2018.

2. B. Niewenhuis, S. Mittal and R. D. Blanton, "Achieving Perfect Multiple-Defect Diagnosis in Regular Circuits," SRC TECHCON 2016, Publication No. P088338, Sept. 13, 2016.

3. B. Niewenhuis, Z. Liu, S. Mittal and R. D. Blanton, "Logic Characterization Vehicle Design for Yield Learning," Annual SEMI Advanced Semiconductor Manufacturing Conference, May 2016.

4. R. D. Blanton, X. Li, K. Mai, D. Marculescu, R. Marculescu, J. Paramesh, J. Schneider and D. Thomas, "Statistical Learning in Chip (SLIC) (Invited Paper)," International Conference on Computer-Aided Design, Nov. 2015.

5. R. D. Blanton, X. Li, K. Mai, D. Marculescu, R. Marculescu, J. Paramesh, J. Schneider and D. Thomas, "SLIC: Statistical Learning in Chip," International Symposium on Integrated Circuits, Dec. 2014.

6. X. Li, R. D. Blanton, P. Grover and D. Thomas, "Ultra-Low-Power Biomedical Circuit Design and Optimization: Catching the Don't Cares," International Symposium on Integrated Circuits, Dec. 2014.

7. Y. Xue, X. Li and R. D. Blanton, "PADRE: Physically-Aware Diagnostic Resolution Enhancement," SRC TECHCON 2013, Publication No. P2291.001, Sept. 9, 2013.

8. C. Xue and R. D. Blanton, "Delay Fault Model Evaluation Using Tester Response Data," International Symposium for Testing and Failure Analysis, Nov. 2012.

9. W. C. Tam, O. Poku, and R. D. Blanton, “Automatic DFM Rule Discovery through Layout Snippet Clustering",IEEE International Workshop on Design for Manufacturability and Yield, June 2010.

10. X. Li, R. Rutenbar, and R. D. Blanton, “Virtual Probe: A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale Integrated Circuits,” ACM International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, Feb. 2009.

11. Y. Lin, O. Poku, N. Bhatti, and R. D. Blanton, “Physically-Aware N-Detect Test Pattern Selection,” SRC TECHCON 2007, Publication P019825, Sept. 2007.

12. J. E. Nelson, W. Maly, and R. D. Blanton, “Diagnosis-Enhanced Extraction of Defect Density and Size Distributions from Digital Logic ICs,” SRC TECHCON 2007, Publication P019906, Sept. 2007.

13. J. Brown and R. D. Blanton, “Diagnosis Automated Testability Enhancements for Logic Brick Libraries,” SRC TECHCON 2007: Invited Session - Focus Center Research Program, Paper FCRP.6, Sept. 2007.

14. T. Zanon, J. Nelson, J. Brown, R. Desineni, N. Patil, W. Maly and R. D. Blanton, “Extraction of Defect Density Size Distributions from Product Test Results,” SRC TECHCON 2005, Oct. 2005.

15. J. E. Nelson and R. D. Blanton, “Multiple-Detect Test Generation Based on Physical Neighborhoods,” SRC TECHCON 2005, Oct. 2005.

16. R. D. Blanton and T. Jiang, “Inductive Fault Analysis of a MEMS Resonator,” MEMS/MST and Their Perspective in Electronic Systems Workshop, March 2005.

17. R. D. Blanton and S. Mitra, “Tutorial: Testing Nanometer Digital Integrated Circuits: Myths, Reality and the Road Ahead,” International Conference on VLSI Design, pp. 8-9, Jan 2005.

18. R. Kundu and R. D. Blanton, “Test Generation for Noise-Induced Switch Failures in Domino Logic Circuits,” SRC TECHCON 2003, Aug. 2003.

19. R. D. Blanton, K. Dwarakanath and A. Shah, “Realistic N-Detect Analysis,” IEEE 12th North Atlantic Test Workshop, May 2003.

20. S. Mir, H. Kerkhoff, R.D. Blanton, H. Bederr and H. Klim, “SoCs with MEMS? Can we include MEMS in the SoCs Design and Test Flow?” IEEE VLSI Test Symposium, p. 449, April 2002.

21. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Relating Buffer-Oriented Microarchitecture Validation to High-Level Pipeline Functionality,” IEEE International High Level Design Validation and Test Workshop, pp. 3–8, Nov. 2001.

22. V. Chickermane, K. Dwarakanath and R. D. Blanton, “Synthesis of HDL Structures for Random Pattern Testability,” International Test Synthesis Workshop, March 2001.

23. R. D. Blanton, “Failure Analysis Using Fault Tuples,” 2nd Annual Latin American Test Workshop, pp. 253–257, Feb. 2001.

24. R. D. Blanton, “The Challenge of MEMS Testing,” IEEE International Test Conference, p. 1133, Oct. 2000.

25. R. Desineni, K. N. Dwarakanath and R. D. Blanton, “Test Analysis Using Fault Tuples,” SRC TECHCON 2000, Publication P000697, Sept. 2000.

26. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Buffer-Oriented Microarchitecture Validation (BMV),” SRC TECHCON 2000, Publication P000713, Sept. 2000.

27. R. Kundu and R. D. Blanton, “Identification of Crosstalk Switch Faults in Domino CMOS Circuits,” SRC TECHCON 2000, Publication P000704, Sept. 2000.

28. R. D. Blanton and B. Courtois, “Guest Editor’s Introduction: MEMS Design and Test,” IEEE Design & Test of Computers, vol. 16,  no. 4,  pp. 16-17,  Oct-Dec,  1999.

29. N. Utamaphethai, R. D. Blanton, J. P. Shen, P. Bose, “Effectiveness Evaluation of the Buffer-Oriented Microarchitecture Validation Methodology,” International Workshop on Microprocessor Test and Verification, Sept. 1999.

30. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Validation of Speculative and Out-of-Order Execution Microarchitecture,” International Workshop on Microprocessor Test and Verification, Oct. 1998.

31. R. D. Blanton, G. K. Fedder and T. Mukherjee, “Hierarchical Design & Test of MEMS,” Microsystems Technology News, no. 1, pp. 28–31, April 1998.

32. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Superscalar Processor Validation at the Microarchitecture Level,” IEEE International High Level Design Validation and Test Workshop, pp. 202–209, Nov. 1997.