Publications
Journal Papers
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J. Sweeney, R. Purdy, R. D. Blanton and L. Pileggi, “CircuitGraph: A Python Package for Boolean Circuits,” The Journal of Open Source Software, Dec. 2020.[PDF]
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Q. Huang, C. Fang, S. Mittal and R. D. Blanton, “Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer,” ACM Transactions on Design Automation of Electronic Systems, vol. 25, no. 5, Aug. 2020.[PDF]
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C. Nguyen, X. Li, R. D. Blanton and X. Li "Partial Bayesian Co-training For Virtual Metrology," in IEEE Transactions on Industrial Informatics, Jan. 2019.[PDF]
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R. Ding, Z. Liu, R. D. Blanton and D. Marculescu, "Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs," in ACM Transactions on Reconfigurable Technology and Systems, 2018.[PDF]
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M. Beckler and R. D. Blanton, "On-Chip Diagnosis of Generalized Delay Failures using Compact Fault Dictionaries," IEEE Transactions on CAD, Feb. 2018.[PDF]
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X. Ren, F. P. Torres, R. D. Blanton and V. G. Tavares, "C Protection Against JTAG-based Attacks," IEEE Transactions on CAD, Feb. 2018.[PDF]
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Y. Xue, X. Li and R. D. Blanton, "Improving Diagnostic Resolution of Failing ICs through Learning," IEEE Transactions on CAD, Sept. 2016. [PDF]
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R. D. Blanton, F. Wang, C. Xue, PK Nag, Y. Xue and X. Li, "DFM Evaluation using IC Diagnosis Data," IEEE Transactions on CAD, July 2016. [PDF]
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H. Wang and R. D. Blanton, "Ensemble Reduction via Logic Minimization," ACM Design Automation of Electronic Systems (TOADES), Vol. 21, No. 4, Sept. 2016. [PDF]
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W. C. Tam and R. D. Blanton, “LASIC: Layout Analysis for Systematic IC-Defect Identification using Clustering,” IEEE Transactions on CAD, Vol. 34, No. 8, Aug. 2016. [PDF]
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W. C. Tam and R. D. Blanton, “Design-for-Manufacturability Assessment for Integrated Circuits using RADAR,” IEEE Transactions on CAD, Vol. 33, No. 10, pp. 1559-1572, Oct. 2014. [PDF]
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S. Biswas, H.-F. Wang and R. D. Blanton, “Reducing Test Cost of Integrated, Heterogeneous Systems using Pass-Fail Test Data Analysis,” ACM Transactions on Design Automation of Electronic Systems, Vol. 19, No. 2, pp. 20:1--20:23, March 2014. [PDF]
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W. C. Tam and R. D. Blanton, “Physically-Aware Analysis of Systematic Defects in Integrated Circuits,” IEEE Design & Test of Computers, Vol. 12, No. 5, pp. 81-93, Sep./Oct. 2012. [PDF]
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X. Yu and R. D. Blanton, “Improving Diagnosis through Failing Behavior Identification,” IEEE Transactions on CAD, Vol. 31, No. 10, pp. 1614-1625, Oct. 2012. [PDF]
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X. Yu and R. D. Blanton, “Diagnosis-assisted Adaptive Test,” IEEE Transactions on CAD, Vol. 31, No. 9, pp. 1405-1416, Sept. 2012. [PDF]
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W. C. Tam and R. D. Blanton, “SLIDER: Simulation of Layout-Injected Defects for Electrical Responses,” IEEE Transactions on CAD, Vol. 31, No. 6, pp. 918-929, June 2012. [PDF]
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R. D. Blanton, W. C. Tam, X. Yu, J. E. Nelson and O. Poku, “Yield Learning through Physically-Aware Diagnosis of IC-Failure Populations,” IEEE Design & Test of Computers, Vol. 29, No. 1, pp. 36-47, Jan./Feb. 2012. [PDF]
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Y.-T. Lin, O. Poku, P. Nigh, P. Lloyd, V. Iyengar and R. D. Blanton, “Physically-Aware N-Detect Test,” IEEE Transactions on CAD, Vol. 31, No. 2, pp. 308-321, Feb. 2012. [PDF]
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W. Zhang, X. Li, F. Liu, E. Acar, R. A. Rutenbar, and R. D. Blanton, “Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits,” IEEE Transactions on CAD, Vol. 30, No. 12, pp. 1814-1827, Dec. 2011. [PDF]
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Y.-T Lin and R. D. Blanton, “METER: Measuring Test Effectiveness Regionally,” IEEE Transactions on CAD, Vol. 30, No. 7, pp. 1058-1071, July 2011. [PDF]
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S. Biswas and R. D. Blanton, “Reducing Test Execution Cost of Integrated, Heterogeneous Systems using Continuous Test Data,” IEEE Transactions on CAD, Volume 30, No. 1, pp. 148-158, Jan. 2011. [PDF]
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D. Ricketts et al, “Enhancing CMOS using Nanoelectronic Devices, a Perspective on Hybrid Integrated Systems,” Proceedings of the IEEE, Vol. 98, No. 12, pp. 2061 – 2075, Dec. 2010. [PDF]
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X. Yu and R. D. Blanton, “Diagnosis of Integrated Circuits with Multiple Defects of Arbitrary Characteristics,” IEEE Transactions on CAD, Vol. 29, No. 6, pp. 977-987, June 2010. [PDF]
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J. G. Brown and R. D. Blanton, “A Built-In Self-Test and Diagnosis Strategy for Chemically-Assembled Electronic Nanotechnology,” Journal of Electronic Testing: Theory and Applications, vol. 23, no. 2/3 pp. 131–144, June 2007. [PDF]
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R. D. Blanton, K. N. Dwarakanath and R. Desineni, “Fault Modeling using Fault Tuples,” IEEE Transactions on CAD, vol. 25, no. 11, pp. 2450-2464, Nov. 2006. [PDF]
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T. Jiang and R. D. Blanton, “Inductive Fault Analysis of Inertial MEMS,” IEEE Transactions on CAD, vol. 25, no. 6, pp. 1104-1116, June 2006.
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S. Biswas and R. D. Blanton, “Statistical Test Compaction Using Binary Decision Trees,” IEEE Design & Testof Computers, vol. 23, no. 6, pp. 452-462, June 2006. [PDF]
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J. E. Nelson, T. Zanon, J. G. Brown, O. Poku, R. D. Blanton, W. Maly, B. Benware and C. Schuermyer, “Extracting Defect Density and Size Distributions from Product ICs,” IEEE Design & Test of Computers, vol. 23, no. 5, pp. 390-400, May 2006. [PDF]
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N. Deb and R. D. Blanton, “Built-in Self Test of MEMS Accelerometers,” IEEE Journal ofMicroelectromechanical Systems,” vol. 15, no. 1, pp. 52-68, Feb. 2006. [PDF]
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R. D. Blanton and J. P. Hayes, “On the Properties of the Input Pattern Fault Model,” ACM Transactions on Design Automation of Electronic Systems, vol. 8, no. 1, pp. 1–17, Jan. 2003.
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K. Heeragu, M. Sharma, R. Kundu and R. D. Blanton, “Test Vector Generation for Charge Sharing Failures in Dynamic Logic,” IEEE Transactions on Computer-Aided Design, vol. 21, no. 12, pp. 1502–1508, Dec. 2002. [PDF]
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R. Arunachalam, R. D. Blanton and L. T. Pileggi, “Accurate Coupling-Centric Timing Analysis Incorporating Temporal and Functional Isolation,” VLSI Design (Special Issue on Timing Analysis and Optimization for DSM ICs), vol. 15, pp. 605-618, 2002. [PDF]
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P. K. Nag, S. Wei, A. Gattiker, R. D. Blanton and W. Maly, “Modeling Economics of Testing: A DFT Perspective,” IEEE Design & Test of Computers, vol. 19, no. 1, pp. 29–41, Jan./Feb. 2001. [PDF]
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N. Deb, S. Iyer, T. Mukherjee and R. D. Blanton, “MEMS Resonator Synthesis for Defect Reduction,” Applied Computational Research Society (ACRS) Journal of Modeling and Simulation of MEMS, vol. 2, no. 1, pp. 11–20, 2001.
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N. Deb and R. D. Blanton, “High-Level Fault Modeling in Surface-Micromachined MEMS,” Kluwer Journal on Analog Integrated Circuits and Signal Processing, vol. 29, no. 1/2, pp. 151–158, Oct./Nov. 2001. [PDF]
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N. Utamaphethai, R. D. Blanton and J. P. Shen, “On the Effectiveness of Microarchitecture Test Program Generation,” IEEE Design & Test of Computers, vol. 17, no. 4, pp. 38–49, Sept.-Dec. 2000. [PDF]
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R. D. Blanton and J. P. Hayes, “On the Design of Fast, Easily Testable ALUs,” IEEE Transactions on VLSI Systems, vol. 8, no. 2, pp. 220–223, April 2000. [PDF]
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N. Utamaphethai, R. D. Blanton and J. P. Shen, “A Buffer-Oriented Methodology for Microarchitecture Validation,” Journal of Electronic Testing: Theory and Applications, vol. 16, no. 1/2, pp. 49–65, Feb. 2000. [PDF]
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T. Mukherjee, R. D. Blanton and G. K. Fedder, “Hierarchical Design and Test of Integrated Microsystems,” IEEE Design & Test of Computers, pp. 18–27, vol. 16, no. 4, Oct.-Dec. 1999. [PDF]
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A. Kolpekwar, T. Jiang and R. D. Blanton, “CARAMEL: Contamination and Reliability Analysis of Microelectromechanical Layout,” IEEE Journal of Microelectromechanical Systems, vol. 8, no. 3, pp. 1–10, Sept. 1999. [PDF]
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C. Bechem, J. Combs, N. Utamaphethai, B. Black, R. D. Blanton and J. P. Shen, “An Integrated Functional Performance Simulator,” IEEE Micro, pp. 26–35, May-June 1999. [PDF]
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R. D. Blanton and J. P. Hayes, “Testability of Divergent Tree Circuits,” Journal of Electronic Testing, no. 11, pp. 197-209, Dec. 1997. [PDF]
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R. D. Blanton and J. P. Hayes, “Testability of Convergent Tree Circuits,” IEEE Transactions on Computers, vol. 45, no. 8, pp. 950–963, Aug. 1996. [PDF]