Publications

Conference Papers

  1. Zeye Liu and R. D. Blanton, "Back-End Layout Reflection for Test Chip Design," in IEEE International Conference on Computer Design, Oct. 2018.[PDF]

  2. Qicheng Huang, Chenlei Fang, Soumya Mittal and R. D. Blanton, "Improving Diagnosis Efficiency via Machine Learning," in IEEE International Test Conference, Oct.-Nov. 2018.[PDF]

  3. X. Ren, R. D. Blanton and V. G. Tavares, "Detection of IJTAG Attacks Using LDPC-based Feature Reduction and Machine Learning", IEEE European Test Symposium, May 2018.[PDF]

  4. S. Mittal and R. D. Blanton, "NOIDA: Noise-resistant Intra-cell Diagnosis," IEEE VLSI Test Symposium, April 2018.[PDF]

  5. S. Mittal and R. D. Blanton, "PADLOC: Physically-Aware Defect Localization and Characterization," IEEE Asian Test Symposium, Nov. 2017.[PDF]

  6. M. Beckler and R. D. Blanton, "Fault Simulation Acceleration for TRAX Dictionary Construction using GPUs," IEEE International Test Conference, Oct.-Nov. 2017.[PDF]

  7. Z. Liu, P. Fynan, and R. D. Blanton, "Front-End Layout Reflection for Test chip Design," IEEE International Test Conference, Oct.-Nov. 2017.[PDF]

  8. C. Nguyen, X. Li, R. D. Blanton, and X. Li, "Partial Co-training for Virtual Metrology," IEEE International Conference on Emerging Technologies and Factory Automation, Sept. 2017.[PDF]

  9. M. Beckler and R. D. Blanton, "GPU-Accelerated Fault Dictionary Generation for the TRAX Fault Model" IEEE International Test Conference Asia, Sept. 2017.[PDF]

  10. R. Ding, Z. Liu R. Shi, D. Marculescu and R. D. Blanton "LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks," ACM Great Lakes Symposium on VLSI, May 2017.[PDF]

  11. X. Lin, R. D. Blanton and D. Thomas, "Random Forest Architectures on FPGA for Multiple Applications," ACM Great Lakes Symposium on VLSI, May 2017.[PDF]

  12. B. Niewenhuis, S. Mittal and R. D. Blanton, "Multiple-Defect Diagnosis for Logic Characterization Vehicles," IEEE European Test Symposium, May 2017.[PDF]

  13. S. Mittal, Z. Liu, B. Niewenhuis and R. D. Blanton, "Test Chip Design for Optimal Cell-Aware Diagnosability", IEEE International Test Conference, Nov. 2016. [PDF]

  14. Y. Xue, C. Lim, M. E. Amyeen, X. Li, and R. D. Blanton, "Diagnostic Resolution Improvement through Learning-Guided Physical Failure Analysis", IEEE International Test Conference, Nov. 2016. [PDF]

  15. P. Fynan, Z. Liu, B. Niewenhuis, S. Mittal, M. Strojwas and R. D. Blanton, "Logic Characterization Vehicle Design Reflection via Layout Rewiring," International Test Conference, Nov. 2016. [PDF]

  16. B. Niewenhuis, S. Mittal and R. D. Blanton, "Achieving Perfect Multiple-Defect Diagnosis in Regular Circuits", SRC TECHCON 2016, Publication No. P088338, Sept. 13, 2016.

  17. X. Ren, R. D. Blanton and V. G. Tavares, "A Learning-based Approach to Secure JTAG against Unseen Scan-based Attacks", IEEE Computer Society Annual Symposium on VLSI, July 2016. [PDF]

  18. B. Niewenhuis, Z. Liu, S. Mittal and R. D. Blanton, "Logic Characterization Vehicle Design for Yield Learning", Annual SEMI Advanced Semiconductor Manufacturing Conference, May 2016. [PDF]

  19. Z. Liu, S. Mittal, B. Niewenhuis and R. D. Blanton, "Achieving 100% Cell-Aware Coverage by Design", Design, Test and Automation in Europe, March 2016. [PDF]

  20. B. Niewenhuis, and R. D. Blanton. “Efficient Built-in Self Test of Regular Logic Characterization Vehicles”, VLSI Test Symposium, Apr. 2015. [PDF]

  21. X. Ren, M. Martin, and R. D. Blanton. "Improving Accuracy of On-chip Diagnosis via Incremental Learning", VLSI Test Symposium, Apr. 2015. [PDF]

  22. X. Ren, V. G. Tavares, and R. D. Blanton. “Detection of Illegitimate Access to JTAG via Statistical Learning in Chip,” Design, Automation and Test in Europe, Mar 2015. [PDF]

  23. R. D. Blanton, B. Niewenhuis, and C. Taylor. “Logic Characterization Vehicle Design for Maximal Information Extraction for Yield Learning”, International Test Conference, Nov. 2014. [PDF]

  24. C. Xue, and R. D. Blanton, “Predicting IC Defect Level using Diagnosis,” Asian Test Symposium, Nov. 2014. [PDF]

  25. John Porche, and R. D. Blanton, “Physically Aware Diagnostic Resolution,” Asian Test Symposium, Nov. 2014. [PDF]

  26. R. D. Blanton, F. Wang, C. Xue, Pk Nag, Y. Xue, and X. Li. "DREAMS: DFM Rule EvAluation Using Manufactured Silicon." International Conference on Computer-Aided Design, 2013. [PDF]

  27. Y. Xue, O. Poku, X. Li and R. D. Blanton, “PADRE: Physically-Aware Diagnostic Resolution Enhancement,” International Test Conference, Nov. 2013. [PDF]

  28. B. Niewenhuis, R. D. Blanton, M. Bhargava, and K. Mai, “SCAN-PUF: A Low Overhead Physically Unclonable Function from Scan Chain Power-Up States,” International Test Conference, Nov. 2013. [PDF]

  29. C. Xue and R. D. Blanton, “Delay Fault Model Evaluation Using Tester Response Data,” International Symposium for Testing and Failure Analysis, Nov. 2012. [PDF]

  30. M. Beckler and R. D. Blanton, “On-Chip Diagnosis for Early-Life and Wear-Out Failures,” International Test Conference, Nov. 2012. [PDF]

  31. H. Wang et. al, “Test Data Volume Optimization for Diagnosis,” Design Automation Conference, June 2012. [PDF]

  32. X. Yu and R. D. Blanton, “Statistical Defect-Detection Analysis of Test Sets using Readily-Available Tester Data,” International Conference on Computer-Aided Design, Nov. 2011. [PDF]

  33. W. C. Tam and R. D. Blanton “Physically-Aware Analysis of Systematic Defects in Integrated Circuits,”International Test Conference, Sept. 2011 [PDF]

  34. W. C. Tam and R. D. Blanton “To DFM or Not to DFM,” Design Automation Conference, June 2011. [PDF]

  35. W. C. Tam and R. D. Blanton “SLIDER: A Fast and Accurate Defect Simulation Framework,” IEEE VLSI Test Symposium, May 2011. [PDF]

  36. W. C. Tam, O. Poku and R. D. Blanton, “Systematic Defect Identification through Layout Snippet Clustering,”International Symposium for Testing and Failure Analysis, ITC Guest Paper, Nov. 2010. [PDF]

  37. J. E. Nelson, W. Tam, and R. D. Blanton, “Automatic Classification of Bridge Defects,” International Test Conference, Oct. 2010. [PDF]

  38. X. Yu and R. D. Blanton, “Estimating Defect-Type Distributions through Volume Diagnosis and Defect Behavior Attribution,” International Test Conference, Oct. 2010. [PDF]

  39. W. C. Tam, O. Poku, and R. D. Blanton, “Systematic Defect Identification through Layout Snippet Clustering,”International Test Conference, Oct. 2010. [PDF]

  40. W. C. Tam, R. D. Blanton, and W. Maly, “Evaluating Yield and Testing Impact of Sub-Wavelength Lithography,” IEEE VLSI Test Symposium, pp. 200-205, May 2010. [PDF]

  41. X. Li, R. Rutenbar, and R. D. Blanton, “Virtual Probe: A Statistically Optimal Framework for Minimum-Cost Silicon Characterization of Nanoscale Integrated Circuits,” IEEE/ACM International Conference on CAD, Nov. 2009. [PDF]

  42. Y.-T. Lin and R. D. Blanton, “Test Effectiveness Evaluation through Analysis of Readily-Available Tester Data,”International Test Conference, Nov. 2009. [PDF]

  43. W.C. Tam and R. D. Blanton, “Automated Failure Population Creation for Validating Integrated Circuit Diagnosis Method,” Design Automation Conference, July 2009. [PDF]

  44. Y.-T. Lin, C. U. Ezekwe and R. D. Blanton, “Physically-Aware N-Detect Test Relaxation,” IEEE VLSI Test Symposium, May 2009. [PDF]

  45. X. Yu, Y.-T. Lin, W. C. Tam, O. Poku and R. D. Blanton, “Controlling DPPM through Volume Diagnosis,” IEEE VLSI Test Symposium, May 2009. [PDF]

  46. S. Biswas and R. D. Blanton, “Maintaining Accuracy of Test Compaction through Adaptive Modeling,” IEEE VLSI Test Symposium, May 2009. [PDF]

  47. S. Biswas and R. D. Blanton, “Improving the Accuracy of Test Compaction through Adaptive Test Update,” IEEE International Test Conference, Oct. 2008. [PDF]

  48. X. Yu and R. D. Blanton, “An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis,” IEEE International Test Conference, Oct. 2008. [PDF]

  49. Y.-T Lin, O. Poku, R. D. Blanton, P. Nigh, P. Lloyd, V. Iyengar, “Evaluating the Effectiveness of Physically-Aware N-Detect Test using In-Production Silicon,” IEEE International Test Conference, Oct. 2008. [PDF]

  50. X. Yu and R. D. Blanton, “Multiple Defect Diagnosis Using No Assumptions on Failing Pattern Characteristics,” Design Automation Conference, June 2008. [PDF]

  51. W. C. Tam, O. Poku and R. D. Blanton, “Precise Failure Localization Using Automated Layout Analysis of Diagnosis Candidates,” Design Automation Conference, June 2008. [PDF]

  52. S. Biswas and R. D. Blanton, “Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data,” Design IEEE VLSI Test Symposium, May 2008. [PDF]

  53. J. G. Brown, B. Taylor, R. D. Blanton and L. Pileggi, “Automated Testability Enhancements for Logic Brick Libraries,” Design, Test and Automation in Europe, March 2008. [PDF]

  54. Y-T. Lin, O. Poku, N. K. Bhatti and R. D. Blanton, “Physically-Aware N-Detect Test Pattern Selection,” Design, Test and Automation in Europe, March 2008. [PDF]

  55. J. G. Brown and R. D. Blanton, “Automated Standard Cell Library Analysis for Improved Defect Modeling,” IEEE International Symposium on Quality Electronic Design, March 2008. [PDF]

  56. O. Poku and R. D. Blanton, “Delay Defect Diagnosis Using Segment Network Faults,” IEEE International Test Conference, Oct. 2007. [PDF]

  57. N. K Bhatti and R. D. Blanton, “Diagnostic Test Generation for Arbitrary Faulty,” IEEE International Test Conference, Oct. 2006. [PDF]

  58. R. Desineni, O. Poku and R. D. Blanton, “A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior,” IEEE International Test Conference, Oct. 2006. [PDF]

  59. J. Nelson and D. Blanton, “Multiple-Detect Test Grading Based on Physical Neighborhoods,” DesignAutomation Conference, pp. 1099-1102, July 2006. [PDF]

  60. J. G. Brown and R. D. Blanton, “Exploiting Regularity for Inductive Fault Analysis,” IEEE VLSI Test Symposium, pp. 364-369, May 2006. [PDF]

  61. J. E. Nelson, T. Zanon, R. Desineni, J. G. Brown, N. Patil, R. D. Blanton and W. Maly, “Extraction of Defect Density and Size Distributions from Wafer Sort Test Results,” Design, Test and Automation in Europe, pp. 913-918, March 2006. [PDF]

  62. R. Desineni and R. D. Blanton, “Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction,” IEEE VLSI Test Symposium, pp. 366- 373, May 2005. [PDF]

  63. S. Biswas, P. Li, R. D. Blanton and L. T. Pileggi, “Specification Test Compaction for Analog Circuits and MEMS,” Design, Test and Automation in Europe, pp. 164-169 March 2005. [PDF]

  64. J. G. Brown and R. D. Blanton, “CAEN-BIST: Testing the Nanofabric,” IEEE International Test Conference, pp. 462-471, Oct. 2004. [PDF]

  65. Vogels et. al, “Benchmarking Diagnosis Algorithms with a Diverse Set of IC Deformations,” IEEE International Test Conference, pp. 508-517, Oct. 2004. [PDF]

  66. N. Deb and R. D. Blanton, “Multi-Modal Built-in Self-Test for Symmetric Microsystems,” IEEE VLSI Test Symposium, pp. 139-147, April 2004. [PDF]

  67. S. Biswas, K. Dwarakanath and R. D. Blanton, “Generalized Sensitization using Fault Tuples,” IEEE VLSI Test Symposium, pp. 297-303, April 2004. [PDF]

  68. C. Liu, K. Chakrabarty, K. Dwarakanath and R. D. Blanton, “Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST,” IEEE Annual Symposium on VLSI, pp. 173 – 178, Feb. 2004. [PDF]

  69. R. Desineni, T. J. Vogels, K. N. Dwarakanath, T. Zanon, R. D. Blanton and W. Maly, “A Multi-Stage Approach to Fault Identification Using Fault Tuples,” International Symposium for Testing and Failure Analysis, pp. 496-505, Nov. 2003.

  70. R. Kundu and R. D. Blanton, “Test Generation for Noise-Induced Switch Failures in Domino CMOS Circuits,” IEEE/ACM International Conference on CAD, pp. 765-768, Nov. 2003.

  71. R. D. Blanton, K. Dwarakanath and A. Shah, “Analyzing the Effectiveness of Multiple-Detect Test Sets,” IEEE International Test Conference, pp. 876-885, Oct. 2003. [PDF]

  72. R. Kundu and R. D. Blanton, “Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk,” IEEE International Test Conference, pp. 122-130, Oct. 2003. [PDF]

  73. W. Maly, A. Gattiker, T. Zanon, T. Storey, T. Vogels and R. D. Blanton, “Deformations of IC Structure in Test and Yield Learning, “ IEEE International Test Conference, pp. 856-865, Oct. 2003. [PDF]

  74. T. Vogels, W. Maly and R. D. Blanton, “Progressive Bridge Identification,” IEEE International Test Conference, pp. 309-318, Oct. 2003. [PDF]

  75. R. D. Blanton, J. T. Chen, R. Desineni, K. Dwarakanath, W. Maly and T. Vogels, “Fault Tuples in Diagnosis of Deep-Submicron Circuits,” IEEE International Test Conference, pp. 233–241, Oct. 2002. [PDF]

  76. N. Deb and R. D. Blanton, “Built-in Self Test for CMOS MEMS,” IEEE International Test Conference, pp. 1075–1084, Oct. 2002. [PDF]

  77. K. Dwarakanath and R. D. Blanton, “Exploiting Equivalence and Dominance Relationships using Fault Tuples,” IEEE VLSI Test Symposium, pp. 269–274, April 2002. [PDF]

  78. R. Kundu and R. D. Blanton, “Timed Test Generation for Crosstalk Switch Failures in Domino CMOS Circuits,” IEEE VLSI Test Symposium, pp. 379–385, April 2002. [PDF]

  79. R. Arunachalam, R. D. Blanton and L. T. Pileggi, “False Coupling Interactions in Static Timing Analysis,” Design Automation Conference, pp. 726–731, June 2001. [PDF]

  80. K. Heeragu, M. Sharma, R. Kundu and R. D. Blanton, “Testing of Dynamic Logic Circuits based on Charge Sharing,” IEEE VLSI Test Symposium, pp. 396–403, April 2001. [PDF]

  81. R. Kundu and R. D. Blanton, “Identification of Crosstalk Switch Faults in Domino Circuits,” IEEE International Test Conference, pp. 502–509, Oct. 2000. [PDF]

  82. R. Desineni, K. Dwarakanath and R. D. Blanton, “Universal Test Generation Using Fault Tuples,” IEEE International Test Conference, pp. 812–819, Oct. 2000. [PDF]

  83. N. Deb and R. D. Blanton, “Analysis of Failure Sources in Surface-Micromachined MEMS,” IEEE International Test Conference, pp. 739–749, Oct. 2000. [PDF]

  84. K. Dwarakanath and R. D. Blanton, “Universal Fault Simulation Using Fault Tuples,” Design Automation Conference, pp. 786–789, June 2000. [PDF]

  85. N. Deb and R. D. Blanton, “High-level Fault Modeling in Surface-Micromachined MEMS,” Design, Test, Integration and Packaging of MEMS/MOEMS, pp. 228–235, April 2000.

  86. T. Jiang and R. D. Blanton, “Particulate Failures for Surface-Micromachined MEMS,” IEEE International Test Conference, pp. 329–337, Sept. 1999. [PDF]

  87. G. K. Fedder and R. D. Blanton, “Characterization and Reliability of CMOS Microstructures,” SPIE Conference on MEMS Reliability for Critical Applications, pp. 132–139, Sept. 1999. [PDF]

  88. T. Jiang, C. Kellen and R. D. Blanton, “Inductive Fault Analysis of a Microresonator,” International Conference on Modeling and Simulation of Microsystems Semiconductors, Sensors and Actuators, pp. 498– 501, April 1999. [PDF]

  89. N. Deb, S. Iyer, T. Mukherjee and R. D. Blanton, “MEMS Resonator Synthesis for Testability,” Symposium on Design Test and Microfabrication of MEMS/MOEMS, pp. 58-69, March 1999.

  90. R. D. Blanton, “IDDQ-Testability of Tree Circuits,” International Conference on VLSI Design, pp. 78–86, Jan. 1999. [PDF]

  91. N. Utamaphethai, R. D. Blanton and J. P. Shen, “Superscalar Processor Validation at the Microarchitecture Level,” International Conference on VLSI Design, pp. 300–305, Jan. 1999. [PDF]

  92. Kolpekwar, R. D. Blanton and S. Woodilla, “Failure Modes for Stiction in Surface-Micromachined MEMS,” IEEE International Test Conference, pp. 551–556, Oct. 1998. [PDF]

  93. Kolpekwar, C. Kellen and R. D. Blanton, “MEMS Fault Model Generation Using CARAMEL,” IEEE International Test Conference, pp. 557–566, Oct. 1998. [PDF]

  94. W. Dougherty and R. D. Blanton, “Using Regression Analysis for GA-Based ATPG Parameter Optimization,” IEEE/ACM International Conference on Computer Design, pp. 516–521, Oct. 1998. [PDF]

  95. R. D. Blanton, S. Goldstein and H. Schmit, “Tunable Fault Tolerance via Test and Reconfiguration,” 28th Annual International Symposium on Fault-Tolerant Computing, pp. 9–10, June 1998. [PDF]

  96. Kolpekwar, C. Kellen and R. D. Blanton, “Fault Model Generation for MEMS,” International Conference on Modeling and Simulation of Microsystems, Semiconductors, Sensors and Actuators, pp. 111– 116, April 1998. [PDF]

  97. R. D. Blanton and J. P. Hayes, “Properties of the Input Pattern Fault Model,” International Conference on Computer Design, pp. 372–380, Oct. 1997. [PDF]

  98. Kolpekwar and R. D. Blanton, “Development of a MEMS-Based Testing Methodology,” IEEE International Test Conference, pp. 923–931, Oct. 1997. [PDF]

  99. S. Wei, P. K. Nag, R. D. Blanton, A. Gattiker and W. Maly, “To DFT or not to DFT?” IEEE International Test Conference, pp. 557–566, Oct. 1997.  Candidate for best-paper award. [PDF]

  100. R. D. Blanton and J. P. Hayes, “The Input Pattern Fault Model and Its Applications,” European Design & Test Conference, p. 628, March 1997. [PDF]

  101. V. D. Agrawal, R. D. Blanton and M. Damiani, “Synthesis of Self-Testing Finite State Machines from High-Level Specifications,” IEEE International Test Conference, pp. 757–766, Oct. 1996. [PDF]

  102. R. D. Blanton and J. P. Hayes, “Design of a Fast, Easily Testable ALU,” IEEE VLSI Test Symposium, pp. 9–16, April 1996. [PDF]

  103. R. D. Blanton and J. P. Hayes, “Efficient Testing of Tree Circuits,” International Symposium on Fault–Tolerant Computing, pp. 176–185, June 1993. [PDF]

Advanced   Chip   
Test  Laboratory.

The Advanced Chip Test Laboratory (ACTL) at Carnegie Mellon University develops and implements data-mining techniques for improving the operation, design, manufacturing and testing of integrated systems. Our research involves data-mining algorithm development, data analysis, chip design and fabrication in collaboration with various industrial partners that currently include IBM, NVIDIA, Qualcomm, CISCO Systems, Intel, GlobalFoundries, and ARM. The founder and head of ACTL is Prof. Shawn Blanton.

Advanced Chip Test Laboratory,

5000 Forbes Ave, Pittsburgh,PA 15213-3890

Tel: 412.268.2987

Email: rblanton@andrew.cmu.edu

ACTL .

© Copyrigh-Advanced Chip Test Laboratory.Updated 4/28/2019